IEEE Semicon Conclave 2025

Heterogeneous Integration and Advanced Packaging in the AI and Edge Era

The rapid evolution of electronic devices has driven the need for advanced packaging solutions that can meet the demands of higher performance, reduced size, and enhanced functionality. Heterogeneous integration in packaging has emerged as a transformative approach, enabling the integration of diverse technologies such as advanced semiconductor chips, passive components, MEMS, sensors, and photonic devices within a single package. This tutorial aims to provide a comprehensive overview of the necessity, benefits, and challenges associated with heterogeneous integration in computing systems, emphasizing its critical role in the future of electronics.

The tutorial would start with explaining foundational economics of building chips with bigger die sizes, defect density, yield, Moore’s law at component level and how disaggregation addresses such challenges. It will then deep dive into Heterogeneous integration, what it means, and various ways of stitching together the building blocks from disaggregation. Commonly used industry terminologies like 2D, 2.5D, 3D will be explained in detail. Despite its numerous advantages, heterogeneous integration also presents several challenges. Issues related to thermal management, signal integrity, mechanical reliability, and interconnect complexity require advanced engineering solutions. The tutorial will delve into these challenges and conclude by giving an overview of technical trade-offs that need to be pro-actively considered to address them.

Puneesh Puri
Principal Engineer Intel Corporation
Arpan Sircar
Senior Principal Engineer, Intel Corporation

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