IEEE Bangalore Section presents
Semicon Conclave 2025
April 12, 2025 | Bangalore, india
Beyond Moore with Chiplets: Co-Optimization for Next-Gen Semiconductors
About the Event
The IEEE Bangalore Semicon Conclave 2025 is a flagship event bringing together industry leaders, academic experts, and professionals to explore the next frontier in semiconductor technology. Scheduled for 12th April 2025 in Bangalore, the conclave will focus on the theme ” Beyond Moore with Chiplets: Co-Optimization for Next-Gen Semiconductors “.
As the semiconductor industry transitions beyond traditional Moore’s Law, chiplet-based architectures are emerging as a game-changer. This conclave will provide a platform to discuss the co-optimization of systems, technology, design, and materials, offering insights into the future of semiconductor innovation.
Guest of Honor
Gokul V Subramaniam
Intel India President & Vice President, Client Computing Group
Keynote Speaker
Dr. Hemanth Jagannathan
IBM Watson Research USA
Plenary Speakers
Prof. Mayank Shrivastava
Professor, IISc Bangalore
Co-Founder, AGNIT Semiconductors Pvt. Ltd.
Biswajit Patra
Fellow and Hardware Platform Architect, Ola Krutrim
Vikas Makhija
Sr Director, R&D
Synopsys India Pvt Ltd
Anindya Saha
VP (Wireless), TEJAS NETWORKS
Deep Tech Talk Speakers
Garima Srivastava
Director, Chip Design
Samsung Semiconductor
Sunil Shrirangrao Kashide
Director, Chip Design Verification
Samsung Semiconductor
Vijaya Kirti Gupta
Director, Samsung Semiconductor India Research
Puneesh Puri
Principal Engineer
Intel Corporation
Arpan Sircar
Senior Principal Engineer, Intel Corporation
Panelists
Mithula Madiraju
STSM, EDA - Routing Methodology
IBM India
Rajeela Deshpande
Associate Director
Samsung Semiconductor
Prabhavathi P
CEO, SkillSOC
Shwetha Kamath
Senior Staff Engineer/Manager, Qualcomm India Private Limited
Shafquat Jahan Ahmed
Group Manager Static Memories, Member Technical Staff , ST Micro
AGENDA
Registration
9:00am - 9:30am
Inauguration
9:30am - 10:00am
Key Note 1
Reimagining Next-Gen Semiconductors – Chiplet and Advanced Packaging in the Era of AI
10.00am – 10.30am
Dr. Hemanth Jagannathan, IBM Watson Research USA
Plenary 1
10.30am - 11.00am
Plenary 2
Universal Chiplet Interconnect Express (UCIe): Enabling paradigm shift towards Multi-Die systems
11.00am – 11.30am
Vikas Makhija, Sr Director, R&D, Synopsys India Pvt Ltd
Tea break and Networking
11.30am – 11.50am
Plenary 3
Chiplets-Driven SoC Design: Powering the Future of AI/ML
11.50pm – 12.20pm
Biswajit Patra, Fellow and Hardware Platform Architect, Ola Krutrim
WIE Panel Discussion
Redefining Semiconductor Scaling : Innovations beyond the Moore’s law
12.20pm – 01.00pm
Mithula, STSM, EDA – Routing Methodology, IBM India
Rajeela, Associate Director, Samsung Semiconductor
Prabhavathi P, CEO, SkillSOC
Shwetha Kamath, Senior Staff Engineer/Manager
Qualcomm India Private Limited
Shafquat Jahan Ahmed, Group Manager Static Memories, Member Technical Staff , ST Micro
Lunch and Networking
01.00pm - 01.45pm
Plenary 4
Standardization Opportunity in Semiconductor Domain
01.45pm - 02.00pm
Anindya Saha, VP (Wireless), TEJAS NETWORKS
Plenary 5
A Roadmap for Disruptive Applications and Heterogeneous Integration Using Two-Dimensional Materials: State-of-the-Art and Technological Challenges
02.00pm - 02.30pm
Prof. Mayank Shrivastava, Professor, IISc Bangalore | Co-Founder, AGNIT Semiconductors Pvt. Ltd.
Deep Techtalk Track 1
Rising to the Challenge: Innovative Solutions for Electronic Design and Verification in era of monlithic design split
02.30pm - 04.00pm
Garima Srivastava, Director, Chip Design, Samsung Semiconductor
Sunil Shrirangrao Kashide, Director, Chip Design Verification, Samsung Semiconductor
Vijaya Kirti Gupta, Director, Samsung Semiconductor India Research
Deep Techtalk Track 2
Heterogeneous Integration and Advanced Packaging in the AI and Edge Era
02.30pm - 04.00pm
Puneesh Puri, Principal Engineer, Intel Corporation
Arpan Sircar, Senior Principal Engineer, Intel Corporation
Quiz/Wrap up
04.00pm - 04.30pm
Tea break and Networking
04.30pm - 05:00pm
Event Highlights
Thought-provoking sessions by industry pioneers and academic experts.
Keynote Talks
Deep dives into the latest advancements in semiconductor technology.
Technical Talks
Engaging conversations on challenges and opportunities in the semiconductor ecosystem.
Panel Discussions
Hands-on learning sessions to enhance technical expertise.
Tutorials
Connect with 200+ professionals, researchers, and industry leaders.
Networking Opportunities
Want to explore all these
Partners
Who Should Attend?
Semiconductor Professionals and Engineers
Researchers and Academicians
Technology Enthusiasts and Students
Industry Leaders and Decision-Makers
Sponsorship
Platinum
Rs. 1,50,000/-
- Product announcement/Tech talk slot (30 min)
- Your company logo displayed in the stage background as Platinum sponsor
- Your company logo displayed on the conference home page as Platinum sponsor
- Your company logo sent out in all mailers as Platinum sponsor
- 15 free delegate registrations
Gold
Rs. 1,00,000/-
- Product announcement/Tech talk slot (20 min)
- Your company logo displayed in the stage background as Gold sponsor
- Your company logo displayed on the conference home page as Gold sponsor
- Your company logo sent out in all mailers as Gold sponsor
- 10 free delegate registrations
Registrations
ORGANISING COMMITTE
Dr. Chandrakanta Kumar
Executive Chair
Dr. Prashant Mishra
Advisory Committee
Abijeet Khopkar
Advisory Committee
Ayan Datta
General Chair
Dr. Chengappa M R
General Chair
Praveen Kumar
Organizing Chair
Jayesh Tanwani
Organizing Chair
Dr. Srobona Mitra
Technical Chair
Vamsi Krishna Addepalli
Publicity Chair
Dr. Mahesh
Finance Chair
